This invention relates to Schottky diodes and to methods for their manufacture. More specifically it relates to Schottky diodes with improved guard rings.
Schottky diodes are used widely in electronic systems such as amplifiers, receivers, control and guidance systems, power and signal monitors, and as rectifiers and clamps in RF circuits. Commercial applications include radiation detectors, imaging devices, and wired and wireless communications products. High frequency Schottky diodes may be GaAs devices, and frequently are discrete devices. RF Schottky diodes can also be silicon devices, which may be integrated in silicon integrated circuits.
To improve leakage characteristics, high performance Schottky diodes are provided with junction guard rings. These devices provide excellent breakdown characteristics in both forward and reverse bias. Conventional junction guarded Schottky diode structures are fabricated by implanting a ring-shaped p-n junction in the semiconductor, typically silicon, forming an oxide surface layer by oxide growth and or deposition, opening a window in the oxide layer, and blanket depositing the Schottky barrier metal. Variations on this method have been proposed, but typically they create the guard ring prior to forming the Schottky metal contact. See e.g. U.S. Pat. Nos. 3,694,719, and 4,607,270. Since prior art Schottky diodes are relatively large, the alignment of the mask for forming the Schottky barrier window has not been critical. Imprecise centering of the window within the guard ring is tolerated.
This fabrication method has drawbacks. For example, misalignment of the Schottky barrier window within the p-n junction guard ring may cause leakage or even breakdown where the guard ring becomes narrow. Making the guard ring large to avoid this potential problem, increases the area required for the device. These limitations of the conventional fabrication method become more consequential as the size of IC devices shrink to meet new manufacturing and IC design demands. Reducing the physical size of the device is an important cost and performance issue. Stray or parasitic capacitance is increasingly consequential as operating frequencies increase. Using a gated structure disconnects the guard ring under nominal forward bias conditions. Whereas this eliminates minority carrier injection so that the device turns off faster thus giving faster switching speeds, there remains a need to develop processing capabilities that allow the size of these devices to be reduced without compromising yield and performance.
I have developed a p-n junction guarded Schottky diode device structure and process for its manufacture that allows precise control the spacing between the guard ring and the Schottky barrier. A key element of the process is the use of a gated guard ring structure of the kind described in principle, and claimed in, my U.S. application Ser. No. 09/273,299, filed Mar. 19, 1999. The distributed guard ring structure according to this invention uses an MOS gate for controlling the spacing between the Schottky barrier and the p-n junction guard ring. The gate is formed first in the process and is used as a self-alignment tool to register the p-n junction guard ring with respect to the Schottky barrier.